A semiconductor test system is to test various types of semiconductor devices by applying test patterns to the semiconductor devices and evaluating resultant output signals from the semiconductor devices. One of the recent semiconductor memories is a synchronous dynamic random access memory (hereinafter referred to as "SDRAM") which is capable of a high speed operation in writing data therein and reading data therefrom.
An SDRAM is a memory that makes a continuous access of the certain range of addresses (memory block) possible by itself by including a special architecture for the continuous access, thereby increasing the overall speed of address access. In a typical SDRAM, a read write rate of 100M byte/sec or higher is possible. For increasing the rate of the continuous access with high speed like this, the continuous read/write of SDRAM is performed in a burst mode. The burst mode is a mode of address access in a memory wherein data in the same row address is read or written continuously for a block consisting of 2, 4, or 8 words or the like. In addition, the access for such words in the block memory is made by simply providing a start address of the block. Afterward, the remaining addresses for the block are generated automatically in the SDRAM by itself.
After receiving the start address, there are two methods for the address sequence of the burst mode; a sequential mode and an interleave mode. FIG. 8 shows an example of two types of burst mode address sequence in an SDRAM in which a burst length is 8 words. In the example of FIG. 8, the numerals in the parentheses are expressed in decimal and the start address is "2". In the sequential mode, the burst address is generated in a continuous sequence while in the interleave mode, the burst address is generated by a sequence based on an exclusive OR logic. When the start address for the continuous access block is provided to the SDRAM, the burst address for the corresponding memory block is produced by the SDRAM either by the sequential mode or the interleave mode. Whether which one of the sequential or interleave mode is used in the SDRAM is predetermined by specifications of the SDRAM in question.
FIGS. 9A and 9B further show examples of the sequential mode bust address and the interleave mode burst address, respectively. In each of the examples of FIGS. 9A and 9B, the top row represented by numerals 1-8 is the order of address generation and the lower rows show the burst address sequence expressed by decimal numbers. In FIG. 9A, eight examples of sequential mode burst address are shown, each of which starts at the start address at the left end. Similarly, in FIG. 9B, eight examples of interleave mode burst address are shown, each of which starts at the start address at the left end.
As noted above, once a start address is received, an SDRAM continuously produces a certain length of wrap address for accessing the memory block therein. In testing such an SDRAM by a semiconductor test system, the same burst address must be generated by the test system for accessing a fail memory to store the test results therein. The test results in the fail memory is used in a failure analysis process of the SDRAM following the test. Thus, the semiconductor test system not only generates start addresses for the SDRAM but also generates the same burst mode address produced in the SDI?AM to be provided to the fail memory.
FIGS. 7A and 7B show an example of address bit allocations at the output of the pattern generator for testing the SDRAM. In this example, a row address of FIG. 7A is produced in the same manner as the row addresses for ordinary memory devices. In FIG. 7B, a part of the column address of the SDRAM is used for generating the burst address. Namely, a set of three LSB (least significant bit) Y0, Y1, Y2 is assigned to produce the predetermined burst address for the memory block in the SDRAM.
FIG. 6 shows an example of pattern generation for testing an SDRAM in the conventional semiconductor test system. This example shows the relationship between the address of the SDRAM 20 to be tested and the corresponding address bits from a pattern generator 10. In this example, the address X0-X11 of the pattern generator is allocated to the row address of the SDRAM. The address Y0-Y2 of the pattern generator 10 is allocated to the burst address for the SDRAM. For the rest of column address of the SDRAM, the address Z0-Z5 of the pattern generator is assigned.
In the pattern generator of the conventional semiconductor test system, it is not possible to generate a complex test pattern including the burst address such as the sequential mode or interleave mode for testing the SDRAM. This is because the standard type semiconductor test system does not include an enough operational ability in the pattern generator to cover the complexity involved in the burst address generation for SDRAMs. Thus, for generating such patterns, it is necessary to pre-install a complex pattern program produced by a mathematical process. In addition to the complexity, in the conventional technology, there is a problem that a start column address for the burst mode operation cannot be produced through an algorithmic procedure.